This invention relates generally to fabrication and packaging of integrated circuit components and, more particularly, to a microwave or millimeter-wave integrated circuit (MMIC) chip attachment process. In complex devices operating at microwave and millimeter-wave frequencies, multiple MMIC chips are typically attached to a single chip carrier or substrate, and interconnected by ribbon or wire bonds. Conventional epoxy techniques for attaching a MMIC chip or die to a substrate prevent chips from being positioned closer than 2 mils (0.002 inch, or approximately 50 μm). Epoxy overflow from beneath the chips may cause input or output pads to be electrically coupled to ground. Therefore, chips must be spaced appropriately to allow for this overflow. The need to use relatively long ribbon lengths between more widely spaced chips results in circuit losses that detract from performance and cause circuit impedance mismatching problems. Ideally, for operation at higher frequencies it would be desirable to position MMIC chips side by side and as close as 0.5 mil apart (0.0005 inch or approximately 13 μm). Similar considerations apply to fabrication techniques used for assembly of other circuit components, such as ball grid array (BGA) devices, which also require precise positioning and attachment of components on a substrate.
Another drawback of the conventional epoxy die attachment technique is that the epoxy may take as long as one to several hours to cure. Ideally, a die attachment process that takes only a few seconds to complete would be preferred because this would drastically reduce cycle time during manufacturing and have a major impact on manufacturing cost.
Yet another drawback of the conventional epoxy die attachment technique is that extraneous organic matter bleeds out onto the substrate and remains in the housing used to contain the substrate and circuit chips. An ideal technique would have a low bleed-out of organic matter and would leave the substrate and housing clean after attachment of the circuit chips.
A further problem with epoxy die attachment is that bonding pads of the chips may crack during the wire bonding process. In the wire bonding process, the chips and substrates are heated to a temperature of approximately 120°-150° C., which softens the epoxy layer between each chip and the substrate. A characteristic of the wire bonding process is that a bonding tool strikes the bonding pad surface with a significant dynamic force to effect a bond. Because the underlying epoxy layer is soft at the required wire bonding temperature, the semiconductor material surrounding and beneath the bonding pad may crack. The process is analogous one in which dynamic force is applied to a thin and brittle material lying on top of a rubber sheet. The rubber sheet provides insufficient mechanical support for the overlying brittle material, which would tend to crack upon application of a dynamic force. Similarly, a semiconductor material supported by an underlying softened epoxy layer tends to crack upon application of a dynamic force. Cracking causes unwanted electrical discontinuities, which significantly affect chip performance, or may render the chip inoperative. An ideal die attachment process would be unaffected by the dynamic forces inherent in wire bonding.
In addition to the foregoing requirements, a die attachment material should provide good electrical and thermal conductivity. Because of the difficulties associated with epoxy for die attachment, soldering processes have been proposed. One such process uses a solder “preform” layer, consisting of quantities of solder applied at precise locations. The preform layer is positioned on the substrate. Then the dies are positioned over the preform layer and the solder is reflowed by the application of heat. One inherent difficulty of this process is that it requires two alignment steps: first aligning the preform layer with the substrate and then aligning the individual dies or chips on the substrate. Therefore, the goal of aligning the dies in close proximity is rendered much more difficult. In addition, the preformed solder is subject to oxidation and, upon reflowing, the oxidation can result in the formation of voids, which are discontinuities in the thermal and electrical transmission paths. Another similar process is referred to as “solder bumping,” in which quantities of tin or tin and lead solder are pre-positioned on the substrate and allowed to cool. When the dies or chips are positioned over the solder bumps, the solder is reflowed by the application of heat. Again there is an inherent problem with oxidation of the solder, resultant void formation and the effects this may have on electrical and thermal resistivity.
It will be appreciated from the foregoing that there is still a need for a die attachment process that provides good electrical and thermal contact, but avoids the known difficulties of attachment by epoxy or using preformed layers or quantities of solder. The present invention meets these requirements.